The invention lies in the semiconductor technology field and pertains, more specifically, to a method for producing a cell of a semiconductor memory.
Semiconductor memories such as DRAMs (Dynamic Random Access Memories) consist of a cell field and a control periphery, with individual memory cells arranged in the cell field.
A DRAM chip contains a matrix of memory cells arranged in rows and columns, which are controlled by word lines and bit lines. Data is written into or read from the memory cells via the activation of suitable word lines and bit lines.
Typically, a memory cell of a DRAM contains a transistor which is connected to a capacitor. The transistor includes two diffusion regions, which are isolated from one another by a channel that is controlled by a gate. One diffusion region is referred to as a drain zone, and the other diffusion region is referred to as a source zone.
One of the diffusion regions is connected to a bit line; the other is connected to a capacitor; and the gate is connected to a word line. By applying appropriate voltages to the gate, the transistor is controlled such that a current flow between the diffusion regions through the channel is switched in and out.
The progressive miniaturization of memory elements gives rise to continually higher integration densities. The continual increase in integration density means that the area available per memory cell grows progressively smaller. In order to effectively exploit the available area, the selection transistor can be formed as a vertical transistor at the sidewall of a trench above a trench capacitor. Memory cells with a vertical selection transistor are known from U.S. Pat. No. 5,744,386, for example. Additional embodiments of trench capacitors and transistors are described in U.S. Pat. No. 5,208,657.
The disadvantage of the memory cells taught by the prior art which have a trench capacitor and a vertical selection transistor, is that they require a cell area of a least 5 F2, where F is the smallest reproducible unit of lithography measurement.
It is accordingly an object of the invention to provide a method for producing a memory cell of a semiconductor memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an alternative with which memory cells with only 4 F2 are possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a memory cell of a semiconductor memory, which comprises the following method steps:
providing a substrate;
forming a first trench in the substrate;
depositing a capacitor dielectric in the trench;
depositing a conductive trench fill in the trench;
sinking the conductive trench fill into the trench;
depositing a first insulating layer on the conductive trench fill in the trench;
overgrowing the first insulating layer epitaxially with an epitaxial layer, proceeding from the substrate;
forming a second trench in the epitaxial layer, the second trench extending through the first insulating layer to the conductive trench fill, and thereby removing a part of the substrate to the conductive trench fill, and forming a ridge from the epitaxial layer;
etching the first insulating layer, thereby undercutting the epitaxial layer;
depositing and sinking a contact layer, whereby the contact layer remains in an undercut region beneath the epitaxial layer;
depositing and sinking a second insulating layer in the second trench;
forming a gate oxide at the ridge;
forming lateral margin ridges as a gate on the gate oxide; incorporating dopant into the ridge, thereby forming a doped region;
forming a bit line on the doped region;
forming a word line over the bit line; and
forming a word line contact for electrically connecting the gate to the word line.
The transistor is formed in the ridge which was structured from the epitaxial layer. The advantage of this is that a floating body effect of the vertical transistor is prevented, since the epitaxial layer is electrically connected to the substrate, and therefore charge can drain into the substrate. Another advantage of the novel process according to the invention is the small cell area of 4 F2, which makes possible an effective exploitation of the substrate surface. Another advantage is that an additional insulation such as an STI in the cell field, which typically insulates an active region, is not required here. Another advantage is that an insulating collar in the trench can be forgone, since there is no parasitic transistor at the outer wall of the trench.
In accordance with an advantageous development of the inventive method, the second trench is so formed that it is off-set from the trench by more than one-third the width of the trench. The staggered formation of the second trench relative to the trench makes possible the inventive electrical connecting of the conductive trench fill to the selection transistor by means of undercutting the epitaxial layer and depositing the contact layer into the undercut region.
In accordance with an additional step in the method, the epitaxial layer is undercut. This creates a hollow space which is suitable for accepting a contact layer.
Another development of the inventive method provides that the contact layer is deposited conformally and then removed from the second trench by a targeted etching technique. With this step, the contact layer remains below the epitaxial layer, it being possible to prevent the eroding of the contact layer through the epitaxial layer with a targeted etching technique.
Another variant of the method provides that the contact layer is formed from doped silicon.
It is also provided that the second insulating layer is deposited conformally on the substrate and in the second trench, leveled by chemical-mechanical polishing, and etched back in the second trench. An insulating layer is thereby formed on the bottom of the second trench which insulates the contact layer from subsequently deposited conductive layers.
A further step provides that, following the sinking of the insulation layer, a sacrificial oxide layer is thermically formed, which is then chemically removed. This technique is suitable for cleaning a silicon surface and eliminating crystal defects thereof, because the top layers of the silicon surface are oxidized, and the oxide layer is then removed. This is suitable for treating the channel surface, on which a gate oxide can then be deposited.
A further step provides that the gate is deposited conformally with a thickness of one-third plus or minus one-sixth the width of the trench, and anisotropically etched, whereby the gate is formed as a lateral margin ridge. This makes it possible to form the gate as a lateral margin ridge in the form of a sleeve around the ridge, the ridge being structured from the epitaxial layer.
A further step provides that an insulating layer is deposited as a bit line sleeve on and at the side of the bit line. This makes it possible to utilize the bit line sleeve as a self-aligned etch mask in subsequent etching steps. A self-aligned formation of the word line contact is therefore possible.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing a cell of a semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.